搜索资源列表
turbo_VHDL
- Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model -Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * M
rs_encoder
- 一个很不错RS编码,用于DVB的信道编码,用VHDL语言编写,在FPGA上通过验证。
xapp514_aes3-audio
- DVB数字音频接口(AESEBU)encoder源码,包括VHDL和VERILOG,基于XILINX FPGA,已验证.-AES-EBU interface,VHDL,VERILOG
ce3100-datasheet
- 机顶盒 set top box 设计参考。intel media processor CE 3100 .功能非常强大!-STB set top box reference design. intel media processor CE 3100. very powerful!
RSOriginal
- Reed-Solomon 信道编码广泛应用于DVB中-Reed-Solomon channel coding are widely used in DVB
Channel_coding_of_dvb-t_system
- DVB_T系统中信道编码的研究与FPGA实现,一篇很好的说是论文,caj阅读器浏览- Research and FPGA Implementation of Channel Coding in DVB-T Systems
RANDOMIZATION
- DVB 数据随机化程序,标准接口,已应用~!-DVB data randomization procedures, standard interfaces, has been applied ~!
SYMBOL_MAPPING
- DVB QAM符号映射!已经应用于产品.标准TS流接口-DVB QAM symbol mapping! Has been applied to products. Standard TS stream interface
CONVOLUTIONAL_INTERLEAVER
- DVB数据交织,交织深度I=12,已得到应用!-DVB data interleaving, interleaving depth I = 12, has been applied!
turbocodes_latest.tar
- 基于sova算法的Turbo码解码VHDL工程文件,非常经典,包含Python高层仿真代码。-Turbo Decoder Release 0.3 MAIN FEATURES - * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizabl